IDT82V3202NLG【PDF 24/117 页】IC PLL WAN EBU SGL 68-VFQFPN

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IDT82V3202

EBU WAN PLL

Pin Description

September 11, 2009

PIN DESCRIPTION

Table 1: Pin Description

Name

Pin No.

(NL68)

Pin No.

(TQFP 64)

I/O

Type

Description 1

Global Control Signal

OSCI

CMOS

OSCI: Crystal Oscillator Master Clock

A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the

master clock for the device.

FF_SRCSW

pull-

down

CMOS

FF_SRCSW: External Fast Selection Enable

During reset, this pin determines the default value of the EXT_SW bit (b4, 0BH) 2. The

EXT_SW bit determines whether the External Fast Selection is enabled.

High: The default value of the EXT_SW bit (b4, 0BH) is ‘1’ (External Fast selection is

enabled);

Low: The default value of the EXT_SW bit (b4, 0BH) is ‘0’ (External Fast selection is dis-

abled).

After reset, this pin selects an input clock for the T0 DPLL if the External Fast selection is

enabled:

High: IN1_CMOS is selected.

Low: IN2_CMOS is selected.

After reset, the input on this pin takes no effect if the External Fast selection is disabled.

SONET/SDH

pull-

down

CMOS

SONET/SDH: SONET / SDH Frequency Selection

During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H):

High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);

Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).

After reset, the value on this pin takes no effect.

RST

pull-up

CMOS

RST: Reset

A low pulse of at least 50 s on this pin resets the device. After this pin is high, the device will

still be held in reset state for 500 ms (typical).

Frame Synchronization Input Signal

EX_SYNC1

pull-

down

CMOS

EX_SYNC1: External Sync Input 1

A 2 kHz, 4 kHz or 8 kHz signal is input on this pin.

EX_SYNC2

pull-

down

CMOS

EX_SYNC2: External Sync Input 2

A 2 kHz, 4 kHz or 8 kHz signal is input on this pin.

Input Clock

IN1_CMOS

pull-

down

CMOS

IN1_CMOS: Input Clock 1

A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,

25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.

IN2_CMOS

pull-

down

CMOS

IN2_CMOS: Input Clock 2

A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,

25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.

Output Frame Synchronization Signal

FRSYNC_8K

CMOS

FRSYNC_8K: 8 kHz Frame Sync Output

An 8 kHz signal is output on this pin.

Output Clock

OUT1_POS

OUT1_NEG

PECL/LVDS

OUT1_POS / OUT1_NEG: Positive / Negative Output Clock 1

A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,

E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,

311.04 MHz or 622.08 MHz clock is differentially output on this pair of pins.

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